YMTC announced the successful development of 128-layer stacked 3D NAND flash memory. X2-6070 has the largest storage density per unit area known in the industry, the 3D QLC with the highest I/O transmission speed and the highest single NAND memory chip capacity, and the 128-layer stacked 3D TLC X2-9060.
The Xtacking architecture adopted by YMTC’s 128-layer stacked products has been fully upgraded to 2.0, which can further release the potential of 3D flash memory. It is based on charge trap (Charge-Trap) storage technology, which can achieve a data transfer rate of 1.6Gbps under 1.2V Vccq voltage. The Xtacking 2.0 architecture of YMTC is currently used to manufacture 128-layer stacked 512Gb 3D TLC NAND flash memory chips, and 128-layer stacked 3D QLC NAND flash memory chips.
The disassembled AN4 1TB SSD uses a 128-layer stacked 512Gb 3D TLC NAND flash memory chip from YMTC. The size is 60.42 square millimeters, and the bit density is increased to 8.48 Gb/square millimeter, which is 92% higher than the Xtacking 1.0 architecture chip (256Gb). YMTC Xtacking hybrid bonding technology uses two wafers to integrate 3D NAND devices, so two dies can be found, one for NAND array chips and the other for CMOS peripheral chips. Its cell structure is composed of two layers, which are connected by a layer interface buffer layer, and the process is the same as that of Kioxia’s 112-layer stacked BiCS 3D NAND flash memory.
Compared with the existing 128-layer stacked 512Gb 3D TLC NAND flash memory products of Samsung (V-NAND), Micron (CTF CuA), and SK Hynix (4D PUC), YMTC’s die size is smaller, which makes it the highest density. Tech Insights believes that YMTC’s 128-layer stacking process is sufficient to compete with other products in terms of capacity, bit density, or I/O speed, and has caught up with other front-runners in technology.