UCIe Consortium releases its 1.1 specification

The UCIe Consortium has announced the public release of the UCIe 1.1 specification, proffering valuable enhancements to the chiplet ecosystem, extending reliability mechanisms to more protocols, and accommodating a broader range of usage models. In light of the automotive industry’s immense market demand for small chiplets adopting UCIe technology, the new standard incorporates additional enhancements tailored for automotive applications, such as fault analysis and operational condition monitoring, while facilitating cost-effective packaging implementation.

In the new version of the specification, the UCIe Consortium elucidates in detail the attributes of the architectural specifications, defining the system settings and registers to be employed in the testing plan and compliance testing. This ensures device interoperability and the UCIe 1.1 specification is fully backward compatible with the original UCIe 1.0 standard. The key points of the UCIe 1.1 specification include:

  • Enhancements targeted at automotive applications, encompassing operational condition monitoring and remediation for high-reliability applications.
  • New applications for streaming protocols with a complete UCIe protocol stack, including simultaneous support for multiple protocols and end-to-end link-layer functionality.
  • Cost optimization for advanced packaging through new bump mapping.
  • Augmented compliance testing.
  • Availability of the UCIe 1.1 specification for public inquiry.

In March of last year, Advanced Semiconductor Engineering, Inc. (ASE), AMD, Arm, Google Cloud, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC announced the establishment of the UCIe Consortium to craft a chiplet ecosystem and to stipulate interconnection standards for small chiplets.

UCIe, standing for Universal Chiplet Interconnect Express, represents an open industry standard designed to establish interconnectivity at the packaging level. The UCIe Consortium aspires to formulate a standard for chip-to-chip interconnection and cultivate an open chiplet ecosystem to satisfy the client’s demands for customizable, package-level integration, connecting chips from multiple suppliers. In the earliest UCIe 1.0 version, it encompassed aspects such as the I/O physical layer between chiplets, protocols, and software stacks, and leveraged high-speed interconnection standards like PCI Express (PCIe) and Compute Express Link (CXL).