TSMC’s 2nm process node will be put into production on time in 2025

Last year, TSMC President Dr. C.C. Wei confirmed that the N2 process node will employ Gate-all-around FETs (GAAFET) transistors as anticipated, with manufacturing still reliant on existing extreme ultraviolet (EUV) lithography technology. Risk production preparations are expected to conclude by the end of 2024, with mass production commencing by the end of 2025, and customers receiving the first batch of 2nm chips in 2026.

A new report from Taiwan online publication MoneyDJ (via Wccftech) shared information from the supply chain, with the latest report indicating that TSMC will begin mass production of 2nm chips in 2025, consistent with the timeline provided by its management. Moreover, TSMC is preparing a new process dubbed N2P, mirroring the naming convention of the 3nm process node; N2P represents an enhanced version of N2, reflecting improvements in production technology.

TSMC has situated its 2nm process node production in the Hsinchu Baoshan factory in Taiwan, which employs the company’s most advanced processes. Additionally, a second factory, known as Fab 20, is being constructed in the Taichung area and will be built in phases. It is understood that the N2P process will utilize backside power delivery (BSPD) technology to enhance performance, an extension of the industry-referred through-silicon vias (TSVs), which allows for stacking and bonding different chip modules together. The new process will further augment the chips’ energy efficiency.

Although TSMC’s 3nm process node will soon enter mass production, Morgan Stanley predicts TSMC’s revenue will decline by 5% to 9% in the second quarter of this year, an increase from the previous 4% downturn. The decline is attributed to a reduction in smartphone chip orders, while TSMC’s expected revenue for 2023 has been downgraded from “modest growth” to “flat.”