TSMC shows its CoWoS packaging technology roadmap
TSMC’s CoWoS (Chip-on-Wafer-on-Substrate) is a 2.5D packaging technology that can package multiple small chips on a substrate. It was first released in 2012. This technology has many advantages, but the main advantages are saving space, enhancing interconnectivity between chips, and reducing power consumption. AMD used the CoWoS package to package the GPU and HBM memory on the Fury and Vega series of graphics cards. Later, NVIDIA also began to use this technology on computing cards such as GP100 and GV100.
After years of development, TSMC, which has grown into a giant in the semiconductor industry, has also made rapid progress in deploying advanced chip packaging technologies. After years of development, TSMC, which has grown into a giant in the semiconductor industry, has also made rapid progress in deploying advanced chip packaging technologies. In ten years, CoWoS packaging has undergone five generations of development. Currently, products using CoWoS packaging are distributed in the consumer and server fields. According to Wccftech reports, TSMC will officially launch the fifth-generation CoWoS packaging solution later this year. The number of transistors will be twenty times that of the third-generation CoWoS package.
The fifth-generation CoWoS package will increase the interposer area three times, eight HBM2E stacks to make the capacity reach 128GB, and there will be a new through silicon via (TSV) solution, etc. Products using this solution will also be seen soon, that is, AMD’s upcoming CDNA 2 architecture product, code-named Aldebaran’s Instinct MI200 computing card. This is also AMD’s first product in MCM (Multi-Chip-Module) multi-chip package, with 16,384 stream processors and 128GB of HBM2E video memory. The Instinct MI200 computing card is planned to be launched in 2022. Next, you can look forward to Nvidia’s products in CoWoS packaging.
TSMC is currently developing a sixth-generation CoWoS packaging solution to integrate more small chips and DRAM chips. The final plan has not yet been determined. It is expected that two computing chips and eight or more HBM3 DRAM chips can be accommodated in the same package. It may be launched in 2023. TSMC will also provide new heat dissipation solutions. The application of new materials will reduce the thermal resistance to 0.15 times the previous value, which will be more conducive to heat dissipation.
