TSMC introduced the FINFLEX technology used in the N3 process
In real life, a series of product designs are the result of compromises, and the chip world is no exception, requiring a balance between performance, power, and cost. For chip designers, it is necessary to select the appropriate semiconductor process technology according to their own positioning.
- 3-2 FIN – Fastest clock frequencies and highest performance for the most demanding compute needs
- 2-2 FIN – Efficient Performance, a good balance between performance, power efficiency, and density
- 2-1 FIN – Ultra Power Efficiency, lowest power consumption, lowest leakage, and highest density
A trend in recent years has been to use processors with a hybrid architecture, where high-performance cores are paired with energy-efficient cores, complemented by various functional modules, TSMC said. With FINFLEX technology, designers can choose the best process configuration for these functional blocks on the same chip, optimizing each block without affecting the others.
Regardless of PPA (power, performance, area), and time-to-market and mass production, plus considering the realization of custom configurations based on FINFLEX technology from the beginning, TSMC believes its N3 process node will be at the leading edge in process technology, offering the widest and most flexible design scope for any product. In addition, TSMC works closely with EDA partners to enable customers to fully utilize FINFLEX technology in their products by using the same toolset.
