TSMC has increased its CoWoS packaging production capacity to 15,000 pieces per month

Over the past few months, the rise of artificial intelligence tools, spearheaded by ChatGPT, has precipitated a significant surge in demand for data center GPUs like Nvidia’s A100 and H100. This surge has strained the advanced packaging capacities of Taiwan Semiconductor Manufacturing Company (TSMC), compelling an urgent expansion of their 2.5D packaging capabilities to meet the burgeoning demand.

TSMC’s 2nm process

According to Wccftech, through TSMC’s continuous efforts, the monthly output for their Chip on Wafer on Substrate (CoWoS) packaging technology has now increased to 15,000 wafers. Of this capacity, Nvidia claims a substantial 40%, while AMD accounts for 8%. The drastic influx of orders from Nvidia has prompted TSMC to initiate corresponding processes earlier this year to bolster the capacity for CoWoS packaging, with rumors suggesting a potential increase to 20,000 wafers per month by the first half of 2024.

When juxtaposed with data previously reported, it becomes evident that the pace at which TSMC has ramped up its CoWoS packaging capacity exceeds initial expectations. Months ago, it was reported that TSMC planned to increase its monthly CoWoS capacity from 8,000 to 11,000 wafers by the end of 2023, and then further to between 14,500 to 16,600 wafers by the end of 2024. Remarkably, TSMC has already achieved these targets ahead of schedule.

Furthermore, TSMC has engaged in partnerships with multiple corporations to outsource some of their packaging orders, a move that could augment their capacity by an additional 20%. This includes companies like ASE Technology Holding and United Microelectronics Corporation (UMC), both of which received orders in September and are now playing pivotal roles in Nvidia’s packaging supply chain. Nvidia is planning to diversify its packaging supply chain and has approached ASE Technology Holding and UMC to provide supplementary technological support, thereby alleviating some of the pressure on TSMC.