Samsung’s 3nm GAA yield rate is only 20%

Samsung announced at the end of June this year that its Huacheng factory in South Korea began to produce 3nm chips, using the new GAA (Gate-All-Around) architecture transistor technology. According to Samsung, compared with the original 5nm process using FinFET, the first-generation 3nm GAA process node has different degrees of improvement in terms of power consumption, performance, and area (PPA), with a 16% reduction in area, a 23% increase in performance, and a 45% reduction in power consumption. By the second generation of 3nm chips, the area has been reduced by 35%, the performance has been increased by 30%, and the power consumption has been reduced by 50%.
Samsung semiconductor R&D center

Although Samsung seems to be one step ahead on the 3nm process node, the actual production is not all smooth sailing. According to ctee reports, like the previous 4/5nm process, Samsung also encountered setbacks in the production of the 3nm GAA process, with a yield rate of only 20%. It is precisely because of Samsung’s poor yield rate on the 4/5nm process that it forces major customers such as Qualcomm to transfer their flagship SoC orders to TSMC.

In order to overcome the numerous obstacles encountered in production, it is rumored that Samsung chose to cooperate with Silicon Frontline Technology in the United States to improve the yield rate of the 3nm GAA process. As for why this company was chosen, it is said that it is an ideal partner to improve the yield rate of wafers through ESD electrostatic and related technologies.

As for whether there are actual benefits, we should also pay attention to Samsung’s foundry situation in the next few months to see if there are customers willing to place orders to adopt Samsung’s advanced technology. It is reported that if Samsung’s plan is successful, Qualcomm may re-select Samsung and adopt a dual-generation factory approach on some SoCs in order to better control production capacity and costs.