Samsung introduces its SF4X process
In recent years, Samsung has funneled substantial capital into its semiconductor manufacturing technology in a bid to rival TSMC, offering its clientele a plethora of viable alternatives and vying for orders ranging from mobile to high-performance computing chips. The 2023 VLSI Technology and Circuit Symposium, scheduled to take place from June 11th to 16th in Kyoto, Japan, will witness Samsung unveiling a process dubbed SF4X, formerly known as 4HPC, specifically engineered for HPC processors.
As per reports from TomsHardware, unlike SF4 (4LPP) which caters to low-power designs for mobile/notebook chips, SF4X boasts superior frequency and efficiency, facilitating the elevated voltages required for high-performance operation. Its salient features include:
Achieving a 10% performance boost while reducing power by 23%, through the application of advanced SD stress engineering, transistor-level DTCO (T-DTCO), and MOL schemes.
Introducing new HPC options, such as ULVT, high-speed SRAM, and high Vdd operation assurance with newly developed MOL schemes. Owing to the novel MOL schemes, the CPU’s minimum voltage (Vmin) stands at 60mV, with a 10% reduction in shut-off current variation. This ensures high voltage (Vdd) operation above 1V without compromising performance, in addition to enhanced SRAM process margins.
SF4X, Samsung’s inaugural process designed expressly for HPC applications, underscores the company’s commitment to this market segment’s potential. The future will see HPC, 5G, and AI forming the industry’s triumvirate trends, commanding substantial demand. Samsung aims to pit SF4X against TSMC’s N4P and N4X; the latter’s scheduled release dates for N4P and N4X are 2024 and 2025 respectively. However, definitive conclusions regarding the technology offering the optimal blend of performance, power, transistor density, efficiency, and cost remain elusive based on the current assertions of foundries alone.