Researchers are developing the next generation of CasFET process

Samsung announced in 2020 that it has conquered the GAAFET all-around gate transistor process, the key technology of the 3nm process node. At the IEEE International Integrated Circuit Conference held in March this year, Samsung introduced the relevant details of the process. This is the successor to the current FinFET fin field-effect transistor process. The transistor has been redesigned, and there are four gates on all sides of the channel. This allows the transistor to have a better insulation design, limits leakage, and allows a lower voltage to be applied under the same switching effect, and also makes the transistors more compact.

CasFET design as shared by Purdue University. The Superlattice layers are the new design breakthrough that could improve transistor miniaturization. (Image credit: Purdue University)

In addition, the structure of the transistor allows designers to precisely adjust the transistor channel width to achieve high performance or low power consumption. Although there is still some time before the GAAFET process is put into mass production, and its improved process is still on the way, the updated CasFET process has already appeared.

According to TomsHardware, researchers at Purdue University are working on silicon-based semiconductors. This new type of transistor called the CasFET process can achieve lower switching voltages, lower power consumption, and higher density designs. Researchers said that “They [transistors] need a high enough ON-current and low enough OFF-current, with a small enough difference to switch between both. These challenges have significantly slowed the downscaling of transistors around the last eight years, making it increasingly difficult to introduce more powerful CPU generations“.

The CasFET process may be the next step in the development of transistors. The superlattice layer is a breakthrough new design that is deployed perpendicular to the transmission direction of the transistor, which can promote the further miniaturization of the transistor and allow for finer voltage control. The research team is currently developing the first transistor prototype using the CasFET process. This work seems to have seen the light, Purdue University has applied for patent protection to the US Patent and Trademark Office.