Rambus Releases PCIe 6.0 Controller: 64 GT/s data rates, PAM4 signaling, FLIT mode

by ddos ·

The PCI-SIG officially released the PCIe 6.0 specification to its members in January 2022, and the new PCIe specification doubles the bandwidth again. PCI-SIG said the release of the PCIe 6.0 specification will benefit data-intensive markets such as high-performance computing (HPC), data centers, edge computing, artificial intelligence and machine learning (AI/ML), automotive, Internet of Things (IoT) aerospace, etc… and further strengthen PCI Express as the interface of high-speed interconnection.

Rambus has announced the world’s first PCIe 6.0 controller, which is fully compliant with the PCIe 6.0 specification released earlier this month. Rambus said the new PCIe 6.0 controller is optimized for power consumption, area, and latency, delivering 64 GT/s data transfer rates for high-performance applications. Additionally, the controller provides state-of-the-art security with an Integrity and Data Encryption (IDE) engine that monitors and protects PCIe links from physical attacks.


Rambus PCIe 6.0 Feature

PCI Express layer

  • Designed to the latest PCI Express 6.0 (64 GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1/3.0 (8 GT/s), and PIPE 6.x (8, 16, 32, 64 and 128-bit) specifications
  • Supports SerDes Architecture PIPE 10b/20b/40b/80b width
  • Supports original PIPE 8b/16b/32b/64b/128b width
  • Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
  • Supports multiple virtual channels (VCs) in FLIT and non-FLIT modes
  • Supports Endpoint, Root-Port, Dual-mode, Switch port configurations
  • Supports PCIe 6.0 to PCIe 1.0 speeds
  • Supports Forward Error Correction (FEC) – Lightweight algorithm for low latency
  • Supports L0p Low Power mode
  • Up to 4-bit parity protection for data path
  • Supports Clock Gating and Power Gating
  • RAS features include LTSSM timers override, ACK/NAK/Replay/UpdateFC timers override, unscrambled PIPE interface access, error injection on Rx and Tx paths, recovery detailed status and much more, allowing for safe and reliable deployment of IP in mission-critical SoCs

User Interface layer

  • Native 256/512/1024-bit Tx/Rx interface
  • User-selectable Transaction/Application Layer clock frequency
  • Sideband signaling for PCIe configuration access, internal status monitoring, debug, and more
  • Optional Transaction Layer bypass

Integrity and Data Encryption (IDE) – Optional

  • Implements the PCI Express IDE ECN
  • Configurable IDE engine
  • Configurable data bus for PCIe IDE
  • Configurable pipeline stages for difference process nodes for best cost and performance balance
  • Supports containment and skid modes
  • Supports multi-stream
  • Utilizes high-performance AES-GCM for encryption, decryption, authentication
  • PCIe IDE TLP aggregation for 1, 2, 4, 8 TLPs
  • PCIe IDE automatic IDE prefix insertion and detection
  • PCIe IDE automatic IDE sync/fail message generation
  • PCRC calculation & validation
  • Efficient key control/refresh
  • Bypass mode

Unique Features & Capabilities

  • Internal data path size automatically scales up or down (256, 512, 1024 bits) based on max. link speed and width for reduced gate count and optimal throughput
  • Dynamically adjustable application layer frequency down to 8 Mhz for increased power savings
  • Optional MSI/MSI-X register remapping to memory for reduced gate count when SR-IOV is implemented
  • Configurable pipelining enables full speed operation on Intel and Xilinx FPGA, full support for production FPGA designs (when supported)
  • Ultra-low Transmit and Receive latency (excl. PHY)
  • Smart buffer management on receive side (Rx Stream) allows implementation of custom credit management schemes in the application logic
  • Merged Replay and Transmit buffer enables lower memory footprint
  • Advanced Reliability, Availability, Serviceability (RAS) features include LTSSM timers override, ACK/NAK/Replay/UpdateFC timers override, unscrambled PIPE interface access, error injection on Rx and Tx paths, recovery detailed status and much more, allowing for safe and reliable deployment of IP in mission-critical SoCs
  • Optional Transaction Layer bypass allows for customer specific transaction layer and application layer
  • Optional QuickBoot mode allows for up to 4x faster link training, cutting system-level simulation time by 20%

Tags: PCIe 6.0 controller