Rambus announced the introduction of a PCI Express (PCIe 6.0) interface subsystem, consisting of PHY and controller IP, while also supporting the latest Compute Express Link (CXL) 3.0 specification. PCIe 6.0 is designed to power next-generation high-performance data centers and AI SoC solutions.
“The rapid advancement of AI/ML and data-intensive workloads is driving the continued evolution of data center architectures requiring ever higher levels of performance,” said Scott Houghton, general manager of Interface IP at Rambus. “The Rambus PCIe 6.0 Interface Subsystem supports the performance requirements of next-generation data centers with premier latency, power, area and security.”
Rambus’ PCIe 6.0 interface subsystem provides a data transfer rate of 64 GT/s and is fully optimized to meet the needs of advanced heterogeneous computing architectures. In this subsystem, the PCIe controller provides state-of-the-art security by having an Integrity and Data Encryption (IDE) engine that monitors and protects the PCIe link from physical attacks.
Since the Rambus PCIe 6.0 interface subsystem fully supports CXL 3.0
, a chip-level solution for cache-coherent memory sharing, scaling and pooling are possible. As CXL becomes more important, and PCIe is ubiquitous in the data center, more customers will pursue continuous upgrades in bandwidth and speed to support next-generation applications, and access to the high-performance interface IP solutions will be an enabler key to the ecosystem.
Key features of the Rambus PCIe 6.0 interface subsystem include:
- Supports PCIe 6.0 specification including 64 GT/s data rate and PAM4 signaling
- Implements low-latency Forward Error Correction (FEC) for link robustness
- Supports fixed-sized FLITs that enable high-bandwidth efficiency
- Backward compatible to PCIe 5.0, 4.0 and 3.0/3.1
- State-of-the-art security with an IDE engine (controller)
- Supports CXL 3.0 for new use models that optimize memory resources (PHY)