Last year AMD was discovered to have a new server socket called “SH5”, according to the analysis of relevant persons, AMD may package the CPU module (Zen 4 architecture CPU) together with the GPU module (Instinct MI200 series GPU) and memory through MCM technology in the future. It is used when building supercomputers. Each node no longer installs CPU, GPU, or even memory separately, and is directly replaced with a chip of SH5 socket.
In fact, AMD published a paper earlier called Design and Analysis of Exascale Computing APUs, which discusses a high-performance chip design, which will include CPU chips, GPU chips, and HBM memory stacks. Obviously, not only AMD is holding the same idea now, but also Intel, which is aggressively attacking the GPU field. During the 2022 investor conference, Intel
announced the new Falcon Shores architecture used on the computing platform, combining x86 CPU cores and Xe-HPC architecture GPU cores in the same socket.
Raja Koduri, senior vice president, chief architect, and general manager of the Architecture, Graphics, and Software Group at Intel, said, the Falcon Shores architecture chips will be integrated into the sockets used by Xeon processors, leveraging next-generation packaging, memory, and I/O technologies that will bring huge performance and efficiency improvements to large-scale computing-intensive and artificial intelligence training model systems.
Intel refers to the Falcon Shores chip as the XPU, emphasizing that it contains two types of computing units, the CPU and the GPU. The Falcon Shores architecture will be designed extensively using Intel’s multi-chip/multi-module approach, according to the needs of the target application, the number of cores of the x86 and Xe-HPC architectures can be flexibly matched. The CPU and GPU will unify the use of high-bandwidth memory to improve performance and simplify programming. Intel seems to be hinting at developing a whole new type of content to work with the Falcon Shores architecture. Products based on the Falcon Shores architecture are expected to be launched in 2024, achieving more than 5x performance improvements in performance per watt, computing density, memory capacity, and bandwidth.