Intel Introduces New Stacked CFET Transistor Architecture

During the recent ITF World 2023 held in Antwerp, Belgium, Ann Kelleher, General Manager of Technology Development at Intel, gave an overview of Intel’s latest advancements in several pivotal areas, one of which is the stacked CFET transistor architecture that Intel will adopt in the future. This represents Intel’s inaugural public introduction of this innovative transistor design, although no specific mass production dates or timetables were disclosed.

In the 2021 online event Intel Accelerates Innovation: Process and Packaging Technology, Intel confirmed that on its Intel 20A process, it would introduce the RibbonFET transistor architecture, designed using the Gate All Around (GAA) concept, replacing the FinFET transistor architecture launched in 2011. This avant-garde technique enhances transistor switching speed while achieving the same drive current as a multi-fin structure, yet occupying a smaller footprint. According to TomsHardware, Ann Kelleher announced that RibbonFET will make its debut next year.

Intel also unveiled the stacked CFET transistor architecture, the next-generation GAA design, permitting the stacking of eight nanosheets, doubling the four nanosheets used in RibbonFET, hence amplifying transistor density. CFET transistors stack n- and pMOS devices on top of each other to achieve higher densities. Intel is currently investigating two types of CFETs, monolithic and sequential, and it seems to have not yet decided which to finally adopt, or whether there will be other design types emerging.

By approximately 2032, transistors will have evolved to 5 angstroms, and changes in the type of CFET transistor architecture would not be unexpected. This time, Intel merely outlined the approximate development trajectory of its transistor technology without sharing many details. More specific information should be released in the future.