GeForce RTX 50 series GPUs will use TSMC’s 3nm process

Currently, NVIDIA’s GeForce RTX 40 series GPUs, based on the Ada Lovelace architecture, do not support key technologies such as DisplayPort 2.1 and PCIe 5.0, leading some users to perceive NVIDIA‘s strategy as somewhat overly conservative.

Recently, insiders revealed that the GeForce RTX 50 series GPUs, based on the Blackwell architecture, will be manufactured using TSMC’s 3nm process. According to TSMC’s previous statements, compared to the existing 5nm process node, the 3nm node can deliver a 15% performance improvement under the same power consumption and transistor count.

Another significant update for the GeForce RTX 50 series GPUs is the support for DisplayPort 2.1, although the specific standard remains unclear. AMD has already introduced support for DisplayPort 2.1 in its existing RDNA 3 architecture-based Radeon RX 7000 series GPUs, meeting the UHBR13.5 link rate requirement (54Gbps). For the Radeon Pro W7000 series GPUs, designed for workstations, they can even support a UHBR20 link rate (80Gbps).

Furthermore, the GeForce RTX 50 series GPUs will also adopt the PCIe 5.0 interface and will be equipped with a new “12V-2×6” connector. The “12V-2×6” connector, based on the upcoming CEM 5.1 specification, features an inward offset of the leading edge changed from the previous 0.45mm to 1.7mm. Compared to the original design, the new connector shortens the sensing pins (the four data pins that define wattage), limiting the power supply if the 12VHPWR cable is not fully connected, to prevent overheating and melting due to excessive power.

According to previous reports, the Blackwell architecture-based GeForce graphics cards will feature five chips: GB202, GB203, GB205, GB206, and GB207. The most significant change from the past is the absence of the GB204 x04 chip after AD104, replaced instead by the x05 GB205 chip.