Chip Giant Leaps Forward: TSMC Prepares 2nm Fab Launch in 2024
Recently, Taiwan Semiconductor Manufacturing Company (TSMC) reiterated at the IEEE International Electron Devices Meeting (IEDM 2023) that its next-generation 2nm process node is set to achieve mass production in 2025. This development will mark the first introduction of Gate-All-Around FETs (GAAFET) transistor technology into its semiconductor processes.
According to a report by LTN, TSMC is gearing up to install equipment in its 2nm wafer fab located in the Hsinchu Science Park in Taiwan. The installation, planned to commence in April 2024, signifies a significant advancement in TSMC’s N2 process project, marking an important milestone. Typically, the equipment installation cycle for a wafer fab spans about a year, including multiple Extreme Ultraviolet (EUV) lithography tools from ASML, followed by a period for validation. As TSMC has never publicly announced a timetable for its 2nm wafer fab, external observers can only glean progress from various subtle indications.
To maintain its leadership in advanced process technology, TSMC has internally formed a team named “One Team,” dedicated to the development, pilot production, and mass production of the 2nm process node. This includes driving synchronous pilot production at its wafer fabs in Hsinchu’s Baoshan and Kaohsiung in Taiwan and aiming for mass production in 2025. The team comprises not only R&D personnel but also engineers from the wafer fabs involved in early-stage production.
Previous reports have indicated that TSMC has made significant investments in northern (Baoshan in Hsinchu), central (Taichung’s Zhongke), and southern (Nanzi in Kaohsiung) Taiwan to construct 2nm wafer fabs. Specifically, in the Hsinchu Science Park’s Baoshan area, Fab 20 is planned, encompassing four 12-inch wafer fabs (P1-P4). This facility is slated to be the starting point for the new generation N2 process, with risk production scheduled to begin in the second half of 2024.
