The CCD area of the Zen 4 architecture EPYC processor is 10.70 x 6.75mm (72.225mm²), the area of the IOD is 24.79 x 16.0mm (396.64mm²), and the package area is 72.0 x 75.40mm (5428mm²). SP5 (LGA 6096) socket area is 76.0 x 80.0mm (6080mm²). Compared with the Zen 3 architecture EPYC processor code-named Milan, the CCD area is reduced by 11%, and the IOD area is also reduced by 5%. However, the package and socket size have become larger, mainly because there are more CCDs in an EPYC processor.
The SP5 socket is the largest socket designed by AMD so far. Compared with the current SP3 socket (4410mm²), not only the area is larger, but also the pins are more than 2002. In addition, the peak power of the SP5 socket is as high as 700W, but it can only last for 1ms. When the power is 440W, it can last for 10ms. In addition to the configuration of up to 96 cores and 192 threads, the EPYC processor code-named Genoa will also have 64 cores, 48 cores, 32 cores, 24 cores, 16 cores, and 8 cores. The next generation of EPYC processors may have models with the highest power configuration of 400W, of which IOD occupies a large part of the power consumption, about 124W, and the remaining 12 CCDs are even less than 280W.
The future competitor of this product will be the Intel Sapphire Rapids Xeon processor, which will also be released in 2022, and will also support PCIe Gen 5 standard and DDR5 memory. Because Intel will add HBM memory to increase memory bandwidth and improve the performance of HPC applications running memory bandwidth-sensitive workloads. It is said that a model equipped with HBM memory will also be launched on the EPYC processor of the Zen 4 architecture. However, AMD is still discussing this issue with its partners, and it seems that it has not made a final decision, and it is likely to adopt a large-capacity 3D V-Cache solution.