AMD to detail 3D V-Cache design
This week will be ISSCC 2022 where AMD will share more details on its 3D V-Cache design. AMD has previously launched a Zen 3 architecture desktop processor with 3D vertical cache technology at CES 2022, that is, the Ryzen 7 5800X3D brings an additional 64MB of 7nm SRAM cache to each CCD, increasing the L3 cache capacity from 32MB to 96MB.
According to Hardwareluxx.de, the 3D V-Cache consists of multiple 8MB “slices” with 1024 interfaces that touch a single CPU core. There are a total of 8192 connection points between CCX and 3D V-Cache, allowing each “slices” to transfer bandwidth up to 2TB/s in full-duplex mode. Although not integrated on CCX, it is likely to be in line with the speed of the native L3 cache. AMD is also said to have improved the design of the Ryzen 7 5800X3D in a number of ways to reduce power consumption and increase frequencies. AMD has yet to confirm when the Ryzen 7 5800X3D will be available, but until the Ryzen 7000 series of the Zen 4 architecture arrives, this is one of the few ways to fight Intel’s Alder Lake.
According to AMD’s presentation, the SRAM that shows the 3D V-Cache is fabricated using TSMC’s N7 process and has an overall size of 41 mm², supported by two additional CCD structures to assist with heat dissipation. In order to fit into the same package, AMD also thinned the original CCD. To allow each core of the processor to communicate with the 3D V-Cache, AMD implemented a shared ring bus design at the L3 level, with the entire L3 cache available to each core.
AMD introduced last year that this 3D chip stacking technology is based on TSMC’s SoIC technology, which mills two chips into a perfect plane. There is a perfect alignment between the bottom layer CCX and the top layer L3 cache, and the TSV channels can be matched without any kind of glue material. To do this, AMD flipped the CCX, shaved off 95% of the top silicon, and mounted the 3D vertical cache chip on top.
