The previously leaked AMD roadmap shows
that in addition to Genoa, the Zen 4c architecture Bergamo, and the next EPYC 7005 series codenamed Turin not only support the SP5 socket but also have a new socket called SP6. The Zen 4 and Zen 4c architecture processors using the SP6 socket will have some limitations in specifications, such as the maximum core count of 32 and 64 respectively, the TDP range between 70W and 225W, and the number of memory, PCIe, and CXL channels have also been reduced.
On the AnandTech Forum
, some netizens exposed the photos and structure diagram of the SP6 socket, which also explained that the new socket is mainly aimed at edge computing and telecom infrastructure applications, and only supports single-channel configuration, so the specifications have been simplified. For these application scenarios, the energy efficiency ratio and performance of the processor are equally important.
The SP6 socket is roughly the same size as the current SP3 socket (58.5 x 75.4 mm) but has a different LGA package, the pin count is 4844, which is significantly smaller/less than the SP5 socket, both in size (76.0 x 80.0 mm) and pin count (6069).
Obviously, the SP3/SP5/SP6 sockets are not compatible with each other, which means that AMD will manufacture two different socket products for each generation of EPYC processors in the future. In addition, some netizens said that the fourth-generation EPYC processor will be divided into two series, namely the EPYC 7004 series, which is positioned for high performance, and the EPYC 5004 series, which focuses on energy consumption ratio.