AMD Ryzen 8000 series feature up to 16 Zen 5 cores
Prior reports have intimated that AMD intends to unveil its innovative Zen 5 architecture in 2024, thereby introducing the Ryzen 8000 series processors. Rumors have it that products based on the Zen 5 architecture may make their debut in the first half of 2024, potentially even in the first quarter.
Recently, PC Games Hardware and Moore’s Law is Dead dispensed some fresh intel regarding the Ryzen 8000 series processors. The kernel codename of AMD’s next-gen desktop platform is ‘Nirvana’, slated to offer products equipped with 6 to 16 cores. The enhancement in performance hinges on the Zen 5 architecture upgrade, with the core cluster adopting a new CCD design named ‘Eldora’.
Given that the range still includes 6 to 16-core products, it is anticipated that the Ryzen 8000 series processor product line will bear striking resemblance to the existing Ryzen 7000 series, while maintaining compatibility with the AM5 platform. Reportedly, the TDP of the Ryzen 8000 series processors will remain within the 65W to 170W range, equipped with up to 16MB of L2 cache and 64MB of L3 cache, possibly employing Taiwan Semiconductor Manufacturing Company’s (TSMC) N3E or N3P fabrication process.
As of now, there have been no updates regarding the Ryzen 8000X3D series processors. However, according to AMD’s CPU product roadmap revealed at a financial analyst event last June, products incorporating 3D vertical cache (3D V-Cache) technology will also be available. There are indications that the eventual release date of Zen 5 architecture products is contingent upon TSMC’s 3/4nm process production supply, factors such as cost, yield, and quality rate being the key considerations, which is one reason why AMD has yet to provide more precise data.
There is speculation that compared to the Zen 4 architecture, the Zen 5 architecture could potentially see a 20% to 25% uplift in IPC, with a frequency boost ranging between 2% to 9%. The substantial IPC increase is largely attributed to changes in the cache structure, with larger caches capable of dispatching more instructions concurrently.
