AMD plans to launch Zen 4 architecture EPYC series processors with HBM memory
At ISC 2021 held last month, Intel introduced a series of technologies and confirmed that Sapphire Rapids Xeon processors can be configured with HBM memory. By adding HBM memory, memory bandwidth can be significantly increased, and the performance of HPC applications running memory bandwidth-sensitive workloads can be improved. If it is not matched with DDR5 memory, it can be used as main memory, if combined with DDR5 memory, it can be used as an L4 cache. It is reported that Sapphire Rapids Xeon processors can be equipped with up to 56 cores and 64GB of HBM2e memory, interconnected by EMIB technology.
Of course, the Intel Sapphire Rapids Xeon processor is not the first manufacturer to choose HBM as its memory. The Fujitsu A64FX processor used by Fugaku, currently the number one supercomputer, has 32GB of HBM2 memory onboard as the main memory. The processor and HBM2 memory are connected through the use of an intermediate module, the structure is similar to the current GPU, and there is no additional configuration of DDR4 memory.
According to Inpact-Hardware, AMD is also planning to launch a model with HBM memory on the EPYC processor code-named Genoa to cope with the Sapphire Rapids Xeon processor with HBM memory. However, AMD is still discussing this issue with its partners, and it seems that it has not yet made a final decision.
It is rumored that AMD will also have an EPYC processor code-named Milan-X before the launch of Zen 4 architecture products. This is similar to the Zen 3 architecture Ryzen processor with 3D V-Cache added to the desktop platform, which improves cache efficiency through 3D stacking technology. This also makes everyone interested in what method AMD will use to integrate HBM memory in the future. In addition to traditional off-chip methods, it may also be achieved through 3D stacking technology.
