AMD recently released a set of EDAC (error detection and correction) driver code patches for the next-generation EPYC series processors based on the Zen 4 architecture. The information contained therein indicates that the new server processors that will be launched next year will have unprecedented memory bandwidth and single-slot capacity in this series.
According to Phoronix, the fourth-generation EPYC processor code-named Genoa (Family 19h Models 10h-1Fh and A0h-AFh) will introduce support for DDR5 RDIMM and LRDIMM. The new generation of EPYC 7004 series processors will support 12-channel DDR5 memory, which is 50% more channels than the current 8-channel. At the same time, the bandwidth of each channel of DDR5 memory is also higher than the current DDR4-3200. For the time being, it is still uncertain how many DIMMs will be in each channel. Earlier news indicated that there would be two.
The increase in the number of channels and the increase in overall bandwidth are not the only improvements in the memory of the next-generation EPYC series processors. At present, Samsung has demonstrated 512GB DDR5 RDIMM and confirmed that 768GB DDR5 RDIMM is feasible, AMD’s next-generation server processors will be able to support up to 6TB of memory. If there are two RDIMMs per channel, the capacity will be doubled. AMD can also use LRDIMMs, so the capacity can be further increased at the expense of performance.