AMD discloses the 3D vertical cache technical details
Recently, AMD shared a video on YouTube’s official account. The content is a more detailed introduction to the 3D Vertical Cache announced at the Taipei Computer Show so that everyone has a deeper understanding of this technology.
AMD 3D chip stacking technology is based on TSMC’s SoIC technology. As a lossless chip stacking technology, it means that no micro bumps or solder are used to connect two chips, and the two chips are milled into a perfect plane. There is a perfect alignment between the bottom layer CCX and the top layer L3 cache, and the TSV channels can be matched without any type of adhesive material. In order to achieve this operation, AMD flipped the CCX (from facing the top to facing the bottom), then cut off the top 95% of the silicon, and then installed the 3D vertical cache chip on it. The advantage is that the distance between the cache and the core is shortened by 1000 times, while the heat, power consumption, and delay are reduced so that the performance is further improved.
At the Taipei Computer Show, AMD has shown the prototype design of the Ryzen9 5900X processor with 3D stacking technology. This innovative technology can bring an additional 64MB 7nm SRAM cache for each CCX, which increases the L3 cache capacity of the processor from 32MB to 96MB, which triples the original capacity. According to official data, after adopting 3D stacking technology, the overall game performance has increased by 15%, which is not small.
AMD has confirmed earlier that later this year, Zen 3 architecture Ryzen series processors equipped with 3D vertical caches will be put into production. It may be the Ryzen 5000XT series processors, I believe I will meet you soon.
