AI Boom Strains TSMC: Chip Demand Outpaces CoWoS Capacity
Due to the unprecedented demand for artificial intelligence (AI) chips, the market’s need for data center GPUs such as Nvidia’s H100 has significantly increased. Consequently, TSMC is continually constructing new facilities to meet customer order demands. With the arrival of Nvidia’s next-generation Blackwell architecture GPUs this year, the demand for CoWoS packaging remains unabated.
According to Trendforce, major cloud services providers like Microsoft, Google, Amazon, and Meta are continuously expanding their AI infrastructure, with this year’s total capital expenditure projected to reach $170 billion. This surge has led to a skyrocketing demand for AI chips and an increase in the silicon interposer area, reducing the number of chips producible from a single 12-inch wafer. As a result, TSMC’s CoWoS capacity remains in short supply.
Nvidia’s forthcoming Blackwell architecture products, including the GB200, B100, and B200, are expected to consume even more CoWoS capacity. Previous reports indicated that TSMC plans to significantly boost packaging capacity in 2024, aiming for a monthly capacity of 40,000 wafers by the end of the year, a 150% increase compared to 2023. Additionally, TSMC is already planning its 2025 CoWoS capacity, likely aiming for a further doubling, with Nvidia’s demand constituting more than half.
Currently, typical CoWoS packaging requires placing multiple HBM chips around the GPU chip, with HBM chips also being considered a bottleneck. As the number of stacking layers and the application of extreme ultraviolet lithography (EUV) increase, the technical difficulty escalates with each iteration of HBM. According to memory manufacturers’ plans, the stacking layers of HBM3/3E will increase from 4 to 8 layers in HBM2/2E to 8 to 12 layers, with HBM4 in the future expected to reach 16 layers.
Given the dual bottlenecks, overcoming the shortage of AI GPU supplies in the short term is challenging. Other foundries are proposing solutions to alleviate packaging capacity shortages, such as Intel’s use of rectangular glass substrates to replace traditional 12-inch wafer interposers, but this requires extensive preparation and collaboration from industry participants.
