Intel claims to achieve trillion-level transistor chip design in 2030

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Recently, Intel announced the latest breakthrough research at IEDM 2022, laying the foundation for future chip design. Its goal is to increase the density of packaging technology by 10 times, use new materials that are only 3 atoms thick to advance transistor scaling, and realize trillion-level transistor chip design in the next 10 years.

This time, Intel researchers demonstrated new 2D materials for transistors, new 3D packaging technologies that close the performance and power gap between chiplets and single-chip processors to an almost imperceptible level, new memory that can be stacked vertically on top of transistors, and more.

“Seventy-five years since the invention of the transistor, innovation driving Moore’s Law continues to address the world’s exponentially increasing demand for computing. At IEDM 2022, Intel is showcasing both the forward-thinking and concrete research advancements needed to break through current and future barriers, deliver to this insatiable demand, and keep Moore’s Law alive and well for years to come,” Gary Patton, Intel vice president, and general manager of Components Research and Design Enablement said.

According to Intel, the next-generation 3D packaging technology based on hybrid bonding can increase the integration density by 10 times, and at the same time reduce the pitch to 3 microns, making multi-chip interconnection comparable to the current single-chip design; using 2D channel material just 3 atoms thick, while achieving near-ideal switching of transistors on a double-gate structure at room temperature with low leakage current. These are two key breakthroughs needed for stacking GAA transistors and moving beyond the fundamental limits of silicon. New memory and stacked ferroelectric capacitors that can be stacked vertically on top of transistors, with performance comparable to traditional ferroelectric trench capacitors, can be used to create FeRAM on logic chips.

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