GB20x Memory Specs Revealed: No 512-bit Upgrade

The GTC 2024 conference is slated to convene from March 18 to 21, 2024, at the San Jose Convention Center in California, USA. Nvidia is anticipated to unveil updates on the Blackwell architecture at this event, primarily focusing on data center products. It’s rumored that the next generation of gaming GPUs will also utilize the Blackwell architecture, though information leaked recently has been relatively scarce.

Recent disclosures from netizens suggest that the GB20x series GPUs will share the same memory interface configuration as the AD10x series, indicating the absence of products with a 512-bit memory bus width. The flagship graphics cards will likely max out at a 384-bit bus width.

Despite the unchanged memory bus width, the next-generation GPUs are expected to support GDDR7, undeniably offering substantially higher bandwidth. Earlier reports have stated that the first GPUs supporting GDDR7 will utilize 16Gb (2GB) modules, and there might also be variants with 24Gb (3GB) modules to enhance memory capacity in the absence of increased memory bus width. Last year, Samsung completed the development of the industry’s first GDDR7 chip, achieving a data I/O rate of 32Gbps per interface. This implies that, even with a 384-bit interface, it would deliver a bandwidth of up to 1.536 TB/s, significantly surpassing the current GeForce RTX 4090’s 1.008 TB/s.

There are indications that the Blackwell architecture will undergo substantial changes, with a new structure for both SMs and CUDA cores. The RT cores might be replaced by PT units, with further optimizations and enhancements to ray tracing performance. It is rumored that the GeForce lineup based on the Blackwell architecture will include five chips: GB202, GB203, GB205, GB206, and GB207, with memory bus widths of 384-bit, 256-bit, 192-bit, 128-bit, and 128-bit, respectively. Notably, after the AD104, there appears to be no GB204 chip, replaced instead by the GB205 in the x05 series.

The GB20x series GPUs are expected to be manufactured using TSMC’s 3nm process technology and will support DisplayPort 2.1 output.