yesterday. You can see that there is a very large branch prediction unit in the Zen 4 architecture. Compared with Zen 3, the micro-operation cache is much larger, and there are load/store units, TLB, branch scheduler, and dual 256bit FPU supporting AVX-512. The L1 cache has not changed, while the L2 cache has doubled in size, occupying a full quarter of the chip area.
also detailed the various caches and latencies of Zen 4 and Zen 3. The processor’s micro-op cache expands from 4K entries to 6.75K entries. The L1 instruction/data cache remains unchanged at 32KB, the L2 cache is expanded from 512KB to 1MB, and the latency is increased from 12 cycles to 14 cycles. The L3 cache size was unchanged, but the latency was increased from 46 to 50 cycles, the reorder buffer was enlarged from 256 to 320 entries, and the L1 branch target buffer was increased from 1KB to 1.5KB.
According to AMD’s data, the CCD area of Zen 4 is 71mm2, while the CCD area of Zen 3 is 80.7mm2, and the chip area is reduced by 12%, but the number of transistors increased from 4.15 billion to 6.57 billion, an increase of 58%, mainly due to the upgrade of the production process from TSMC 7nm to 5nm.
The IOD has also changed a lot. Previously, the IODs used in the Zen 2 and Zen 3 processors were produced by GF’s 12nm process. Now, the IODs used in the Zen 4 processor have been changed to TSMC’s 6nm process. The improvement is very large. The old IOD chip area is 125mm2, while the new IOD area is 122mm2, and the size is slightly reduced. In addition to the DDR5 memory controller and PCI-E 5.0 controller, the new IOD also has an iGPU with two sets of RDNA2 architecture CUs and integrates some power management functions of the Rembrandt architecture of the Ryzen 6000 series.