AMD confirms ‘Strix Halo’ APU: equipped with 16 Zen 5 cores and 40 sets of RDNA 3.5 architecture CUs
Recently, AMD submitted new patches to the ROCm open-source computing platform. In addition to the previously mentioned “GFX1150” and “GFX1151” Strix codes, it also introduced, for the first time alongside a GPU ID, a chip referred to as “STRIX1” from the “Strix Point” series, adhering to the naming convention established by “PHOENIX1.” Strix Point has long been a codename for a highly anticipated APU.
From the information circulated earlier, Strix Point is expected to come in two designs. The first adheres to the conventional single-die architecture, incorporating a hybrid architecture of Zen 5+Zen 5c for the CPU section and increasing the Compute Unit (CU) count to 16 in the GPU section. The second variant, possibly termed “Strix Point Halo” or “Sarlak,” represents a high-end APU employing a chiplet design. This variant could feature up to 16 cores in the CPU section and offer 40 CUs in the GPU section, based on the RDNA 3.5/3+ architecture, allowing it to compete with some of Nvidia’s mobile discrete GPUs in terms of graphical performance.
Strix Point Specifications:
- Single-die design, 4nm process
- Hybrid architecture of Zen 5+Zen 5c, up to 12 cores
- 32MB of shared L3 cache
- 128-bit LPDDR5X memory controller
- RDNA 3.5/3+ architecture, 16 CUs
- Integrated XDNA architecture AI engine, achieving 20TOPS
Strix Point Halo Specifications:
- Chiplet design, 4nm process
- Zen 5 architecture, up to 16 cores
- 64MB of shared L3 cache
- 256-bit LPDDR5X memory controller
- RDNA 3.5/3+ architecture, 40 CUs
- Integrated XDNA architecture AI engine, achieving 40TOPS
Although reports previously suggested that both Strix Point and Strix Point Halo would be launched within 2024, the latest indications suggest AMD may delay their release to 2025, incorporating them into the Ryzen 9000 series product line.
