Cadence releases PCIe 6.0 IP test chip design kit
About a month ago, PCI-SIG announced that PCIe 6.0 has reached version 0.9, which is equivalent to the final draft stage. Currently, PCI-SIG members are conducting internal reviews of the technology to ensure their intellectual property rights and patents. Unless there is a major problem, no functional modification is allowed, and relevant companies can also start to adopt PCIe 6.0 in their products.
Recently, Cadence announced the launch of the PCIe 6.0 IP test chip design kit, allowing chip developers to implement PCIe 6.0 support and test in their designs. It supports Cadence’s Intelligent System Design strategy and realizes the outstanding design of SoC. According to Cadence, early developers have begun to explore a new generation of PCIe 6.0 specifications, using Cadence and TSMC technology, which may be added to the chip design in 2022-2023
This PCIe 6.0 IP test chip design kit includes a DSP-based high-performance PHY and a feature-rich supporting controller, providing optimized performance and throughput for next-generation applications of ultra-large-scale computing and 5G communications. In July of this year, Cadence’s PCIe 6.0 subsystem test chip was taped out on TSMC’s N5 process node. It integrates the second-generation power, performance, and area (PPA) optimized PCIe 6.0 PHY and PCIe 6.0 controller.
“Early adopters have already started exploring with the new PCIe6 specification, and we are looking forward to seeing them achieve positive results with TSMC and Cadence technologies,” said Sanjive Agarwala, corporate vice president and general manager of the IP Group at Cadence. “We’ve been deploying PAM4-based IP since 2019 when we introduced our first-generation 112G-LR SerDes IP, and our vast expertise in PAM4 technology plus our strong collaboration with TSMC provides a robust foundation for success with our PCIe6 products.”
