AMD further explained the 3D packaging technology
On Hot Chips 33, AMD talked about the development direction of its 3D stack technology, and also shared some details of the 3D V-Cache. AMD said that package selection and chip architecture depend on the performance, power, area, and cost of the specific product, which AMD calls PPAC. If the already released and upcoming products are included, AMD has 14 kinds of multi-layer chiplet design package architectures in progress.
According to ComputerBase, AMD’s senior researcher in charge of packaging Raja Swaminathan said that not every solution is suitable for all products. The future belongs to modular design and matching and coordinated packaging. This is the consensus of the industry, and the solutions displayed by various manufacturers have proved this point. However, all manufacturers pay attention to economic benefits. Not all solutions are suitable for the consumer market. For example, Zen 3 architecture desktop processors equipped with 3D vertical cache (3D V-Cache) technology require at least a 12-core processor to be used.
In June, AMD introduced that its 3D vertical cache technology is based on TSMC’s SoIC technology. With the increase of through silicon vias (TSV), AMD will focus on more complex 3D stacking technologies in the future, such as core stacking core, IP stacking IP, and even macroblocks that can be 3D stacked. Eventually, the spacing of the through silicon vias will become very tight, so that module splitting, folding and even circuit splitting will become possible, which will completely change today’s perception of processors.
AMD shared some information about the 3D V-Cache technology used on the Zen 3 architecture processor, which uses 3D micro bumps and through silicon via interconnection schemes, combined with a new hydrophilic dielectric bonding and Direct CU-CU bonding technology. The pitch of the hybrid bonding is only 9u, which is smaller than the 10u pitch of Intel Forveros interconnect. AMD expects its 3D Chiplet technology to provide 3 times the interconnect energy efficiency and 15 times the interconnect density.
