TSMC develops 2nm process, Meet the needs of Apple and Nvidia

In the preceding year, TSMC’s President Wei Zhejia confirmed that the 2nm process node will, as anticipated, employ Gate-all-around FETs (GAAFET) transistors. The fabrication process continues to rely on the extant extreme ultraviolet (EUV) lithographic technology, with preparations for risk production projected to be complete by the end of 2024, advancing to mass production by the close of 2025. Consequently, customers will receive the inaugural batch of chips manufactured through the N2 process in 2026.

According to reports from UDN, TSMC is unreservedly committed and has initiated the preparatory work for the pilot production of the 2nm chips. This drive is two-pronged: to sustain the lead over Samsung and Intel and to fulfill the manufacturing requirements stipulated by Apple and NVIDIA.

Informants disclose that TSMC has dispatched engineers and support staff to its research and development factory in the Hsinchu Science Park, Taiwan, to prepare for the 2nm trial production. This year, TSMC will establish a small-scale production line with the objective of manufacturing a thousand wafers, setting the stage for trial production in 2024. Should all go according to plan, TSMC will expand the production line of the new factory. In light of the introduction of the novel GAA transistors in the N2 process for the first time, the likelihood of unforeseen circumstances warrants early commencement of production.

With the transformation of the market environment, customer competition has intensified more than ever before. TSMC’s primary collaborators are actively investing in tailored solutions to ensure seamless production and superior chip performance. TSMC has further integrated artificial intelligence into its manufacturing processes to enhance efficiency and conserve energy, thereby reducing carbon emissions. In addition, TSMC has readied N2P and N2X processes for the 2nm process node to cater to diverse chip manufacturing demands.