TSMC announces 2nm & 3nm process technology roadmap
Recently, at the 2023 North America Technology Symposium held in Santa Clara, California, TSMC presented a roadmap for advanced semiconductor manufacturing processes, encompassing various 3nm and 2nm process nodes.
According to Wccftech, TSMC will launch an improved N3E process this year, offering lower costs and enhanced economic benefits. Subsequently, a broader product portfolio will be provided at the 3nm process node, including N3P, N3X, and N3AE, catering to diverse customer requirements:
- N3P – An enhanced 3nm process scheduled for production in the latter half of 2024, offering additional improvements over N3E, increasing speed by 5% at the same power, or reducing power consumption by 5%-10%, with a 1.04x increase in density.
- N3X – Prioritizing HPC application performance and maximum frequency, N3X delivers a 5% speed improvement over N3P at 1.2V, maintaining the same density, and entering mass production in 2025.
- N3AE – Standing for “Auto Early,” to be launched in 2023, providing an automotive process design kit (PDK) based on N3E, allowing customers to introduce designs for automotive applications at the 3nm process node and launching a fully automotive-compliant N3A process in 2025.
TSMC continues to make steady progress in the technological development of its 2nm process node, adopting the GAAFET (Gate-All-Around FET) transistor architecture and making strides in yield and performance. TSMC anticipates launching the N2 process in 2025, increasing speed by 15% compared to N3E at the same power or reducing power consumption by 30%, with a 1.15x increase in density.
TSMC is also developing N4PRF, pushing the boundaries of CMOS radio frequency technology, expected to become the industry’s most advanced CMOS radio frequency solution for digitally-intensive radio frequency applications, such as Wi-Fi 7 RF system chips. Compared to the N6RF released in 2021, logic density increases by 77% at the same speed, with a 45% reduction in power consumption.
