SK Hynix showcases HBM3 at the OCP Summit
At the end of last month, SK Hynix announced that they have successfully developed HBM3 DRAM memory, and they brought the finished product to the OCP Summit for display. This sample of HBM3 was photographed by ServeTheHome.
In fact, JEDEC is responsible for the HBM3 specification, and the final specification has not been announced yet. SK Hynix’s HBM3 memory can provide two capacities, one is 24GB with 12-layer TSV technology vertically stacked, and the other is 16GB with 8-layer stacked. The displayed sample is 12-layer, the memory frequency can reach 6400Mbps, and the bandwidth provided by a single stack can reach 819GB/s, which is much higher than the previous generation of HBM2E memory 461GB/s.
Compared with HBM2E, HBM3 not only provides higher bandwidth but also stacks more layers of DRAM to increase capacity. HBM3 memory also has built-in on-chip error correction technology, which significantly improves product reliability.
HBM is unlikely to replace traditional DRAM memory in the consumer market in the short term because its price is too expensive, but it still has a lot to do in the field of high-performance computing. It is expected that HBM3 will be mainly used in high-performance data centers and machine learning platforms to improve the level of artificial intelligence and the performance of supercomputers, which can be used for climate change analysis and drug development.