Intel Explains Ponte Vecchio: A total of 63 modules, TDP up to 600W
Intel will be giving a more in-depth presentation on the upcoming Ponte Vecchio during ISSCC 2022. This is Intel’s first computing GPU, using Intel’s most advanced packaging technology ever, with more than 100 billion transistors, it is composed of 47 Tiles is the culmination of Intel’s advanced technology at this stage.
As reported by Hardwareluxx.de, Intel’s presentation at ISSCC 2022 showed the structure of Ponte Vecchio. It is slightly different from the previous statement, showing a total of 63 modules. In addition to the original 16 Xe-HPG architecture computing chips, 8 Rambo cache chips, 2 Xe base chips, 11 EMIB connection chips, 2 Xe Link I/O chips, and 8 HBM chips, there are also 16 for TDP output, integrated into the Foveros 3D package via EMIB.
Intel introduced the situation of Rambo cache, this new SRAM technology is a module composed of four sets of 3.75MB (15MB in total) cache, each chip has a connection speed of 1.3 TB/s, and 8 Rambo cache chips can bring an additional 120MB of SRAM. The Xe base chip has an area of 646 square millimeters, with a total of 17 layers, including the memory controller, fully integrated voltage regulator (FIVR), power management, and 16-lane PCIe 5.0 and CXL interfaces.
Ponte Vecchio’s computing chip uses TSMC’s N5 process, and the Xe Link I/O chip uses TSMC’s N7 process. The Xe base chip and Rambo cache chip use the Intel 7 process, and the entire package size reaches 4843.7 square millimeters. In addition, the TDP of Ponte Vecchio is 450W. If the cooling method is changed from air cooling to water cooling, the TDP can be increased to 600W.
