Intel demonstrates the world’s first UCIe-connected chiplet-based processor

At the “Intel Innovation” summit held in San Jose, California, Intel’s CEO Pat Gelsinger showcased the world’s inaugural chip utilizing UCIe connectivity.

According to TomsHardware, this UCIe-connected chip boasts an Intel 3 process-manufactured UCIe IP module. Additionally, it integrates a Synopsys UCIe IP module crafted through TSMC’s N3E process. Intel’s sophisticated EMIB packaging technology bridges these two modules.

Image credit: Tom’s Hardware

In March 2022, Advanced Semiconductor Engineering, Inc. (ASE), AMD, Arm, Google Cloud, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC heralded the establishment of the UCIe consortium. This alliance aspires to cultivate a chiplet ecosystem and delineate chiplet interconnect standards, thus facilitating seamless collaboration between modules from diverse manufacturers. The latest iteration is the UCIe 1.1 specification, which, besides supporting the standard 2D packaging, also endorses advanced 2.5D packaging solutions like Intel’s EMIB and TSMC’s CoWoS.

UCIe, or Universal Chiplet Interconnect Express, denotes a universal interconnect pathway for chiplets. As an open industry standard, its purpose is to forge interconnections at the packaging level. The UCIe alliance envisions instituting a chip-to-chip interconnect standard and fostering an open chiplet ecosystem, addressing the demand for customizable package-level integrations, and linking chips from a multitude of suppliers. In its nascent UCIe 1.0 version, it encompassed the I/O physical layer, protocols, and software stack between chiplets, leveraging high-speed interconnect standards like PCI Express (PCIe) and Compute Express Link (CXL).