According to Wccftech
, Rialto Bridge can be seen as an optimized and upgraded version of Ponte Vecchio. The number of Xe cores has increased from 128 to 160, and the I/O bandwidth will also increase. It is possible to use HBM3, which may be the second data center GPU accelerator using HBM3 after the NVIDIA Hopper architecture. The Rialto Bridge will use OAM v2 modules with a TDP of up to 800W. Intel promises that the Rialto Bridge will be compatible with the Ponte Vecchio subsystem, maintaining software consistency.
Intel claims that Rialto Bridge will use a new process to manufacture modules with higher density, performance, and energy efficiency, but did not confirm the specific process. It is speculated that it is possible to use an Intel 4
. According to industry analysts, Rialto Bridge may cancel the separate Rambo cache chip and choose to integrate it into the computing chip.
Following is the full Intel Rialto Bridge die configuration that we can dissect at the moment:
- 8 Xe HPC (internal/external)
- 2 Xe Base (internal)
- 11 EMIB (internal)
- 2 Xe Link (external)
- 8 HBM (external)
Intel hasn’t given any release time or details regarding the process node for the Rialto Bridge GPU but it is likely that we will hear more about it in mid-2023 when it will be sampled to first customers and a launch that aims either late 2023 or 1H of 2024.