AMD has applied for the 3D V-Cache trademark
In this year’s Computex 2021 keynote speech, AMD CEO Dr. Lisa Su demonstrated the Zen 3 architecture desktop processor with 3D vertical cache (3D V-Cache) technology. This is the first time people have seen the use of AMD technology. This innovative technology can bring an additional 64MB 7nm SRAM cache for each CCD, which increases the L3 cache capacity of the processor from 32MB to 96MB, which triples the original capacity.
“File:AMD CEO Lisa Su 20150603.jpg” by Gene Wang is licensed under CC BY 2.0
Recently, AMD has applied to the US Patent and Trademark Office for the 3D V-Cache trademark, which will be the name of a consumer-oriented stacking cache solution. On Hot Chips 33 this year, AMD stated that this technology will eventually change the design of future processors.
According to AMD’s official introduction, the 3D vertical cache technology is based on TSMC’s SoIC technology. As a lossless chip stacking technology, it means that no micro bumps or solder are used to connect two chips, and the two chips are milled into a perfect plane. At present, the technology is only used on the CPU. The recent release of EPYC processor code-named Milan-X means that 3D V-Cache technology is officially on the market.
In order to meet the needs of future use, general companies will cover all possible scopes when applying for trademarks to better protect their intellectual property rights from infringement. According to previous rumors, AMD is likely to introduce a 3D stack design to the design of Infinity Cache. Perhaps 3D V-Cache technology will be used more widely in the future, and the technical application scope of AMD’s application this time also covers SoC, SSD, DRAM, etc.
