In Intel’s recently released Alder Lake Developer Guide, they disclosed some previously undisclosed information, including general SKU and instruction set support. Because Alder Lake is composed of two different architecture cores, Golden Cove (P-Core) and Gracemont (E-Core), it will have more different core combinations than previous processors.
The core code name of the desktop version is Alder Lake-S. The flagship core is composed of 8 P-Cores plus 8 E-Cores, equipped with 32 sets of EU, while the other core has only 6 P-Cores, and is equipped with 32 sets of EU. According to the previous gossip, Core i5-12600K and higher models will use the previous hybrid core, while Core i5-12600 and below models will use only P-Core cores.
The mobile version has changed the previous core classification of U and H and is collectively called Alder Lake-P. Of course, the specific processor model will still be divided into U and H. Unlike the desktop version, the mobile version of Alder Lake-P all have E-Cores, and the Alder Lake-P that replaces Tiger Lake-U has 2 P-Cores and 8 E-Cores, instead of Tiger Lake-H, there are up to 6 P-Core and 8 E-Core.
According to the schematic diagram given by Intel, each P-Core has its own L2 cache and is directly connected to the L3 cache, E-Core is a group of 4, sharing an L2 cache and then connecting to L3.
Regarding the instruction set, Golden Cove supports AVX512, but Gracemont does not, so the current Intel solution is that AVX512 will be disabled when E-Core is enabled and whether the AVX512 switch is given or not can be determined by the OEM. TSX instruction set is directly disabled, other AVX-VNNI, vAES, vCLMUL, and UMWAIT/TPAUSE can be added by ISA.